HDL approach to board-level BIST

Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed...

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Bibliographic Details
Main Author: Gustavo R. Alves (author)
Other Authors: Manuel G. Gericota (author), José L. Ramalho (author), José M. M. Ferreira (author)
Format: book
Language:eng
Published: 1993
Subjects:
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Online Access:https://repositorio-aberto.up.pt/handle/10216/84553
Country:Portugal
Oai:oai:repositorio-aberto.up.pt:10216/84553
Description
Summary:Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.

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