Gerador de padrões de vídeo UHD utilizando HDL (Verilog)
The present dissertation consists of the implementation in a FPGA, using HDL (Verilog) and existing IP Cores, of a Video Pattern Generator for high resolutions as is the case of 4K and 8K, at 60 frames per second (fps). The frames generated by the Video Pattern Generatore are sent to the SDI interfa...
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| Formato: | masterThesis |
| Idioma: | por |
| Publicado em: |
2019
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| Assuntos: | |
| Texto completo: | https://hdl.handle.net/10216/121199 |
| País: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/121199 |