Synthesis of combinational logic circuits using genetic algorithms
This paper proposes a genetic algorithm for designing combinational logic circuits and studies three different case examples: the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gate...
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| Format: | conferenceObject |
| Language: | eng |
| Published: |
2019
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| Online Access: | http://hdl.handle.net/10400.22/13322 |
| Country: | Portugal |
| Oai: | oai:recipp.ipp.pt:10400.22/13322 |
| Summary: | This paper proposes a genetic algorithm for designing combinational logic circuits and studies three different case examples: the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates. |
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