An automated verification process based on scan techniques
Matching the results achieved during circuit simulation with those extracted from circuit operation is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against...
| Autor principal: | |
|---|---|
| Outros Autores: | , , |
| Formato: | book |
| Idioma: | eng |
| Publicado em: |
2000
|
| Assuntos: | |
| Texto completo: | https://hdl.handle.net/10216/84994 |
| País: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/84994 |