An automated verification process based on scan techniques
Matching the results achieved during circuit simulation with those extracted from circuit operation is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against...
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| Other Authors: | , , |
| Format: | book |
| Language: | eng |
| Published: |
2000
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10216/84994 |
| Country: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/84994 |