| Resumo: | Computer architecture is an important subject for informatics and electrical engineering courses, where students get to know how a CPU works internally. However, the students exhibit some difficulties in this subject. This is due to the lack of versatile educational tools that simulate the operation of a processor in an intuitive, integrated, graphical and configurable way. One of the most used processor architectures for teaching computer architecture is MIPS. The architecture has a few different versions, but the most used for teaching are the unicycle and the 5-stage pipeline. In this dissertation, an educational MIPS simulator, DrMIPS, is described. This tool simulates the execution of an assembly program on the CPU, step-by-step, and displays the status of the datapath graphically. Registers, data memory and assembled code are also displayed, and a "performance mode" for latencies and critical path analysis is also provided. Both unicycle and pipeline implementations are supported and the CPUs and their instruction sets are configurable. The pipeline implementation includes complete hazard detection and resolution. The tool seeks to help students to understand topics like the composition and operation of a datapath, pipelining, instruction encoding and processor measuring. It is available not only for PCs but also for Android tablets. None of the other existing tools have a version for Android and this is a platform that is becoming very popular. The tool supports multiple languages and is fairly intuitive and versatile on both platforms.
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