Logic-based schedulability analysis for compositional hard real-time embedded systems
Over the past decades several approaches for schedulability analysis have been proposed for both uni-processor and multi-processor real-time systems. Although different techniques are employed, very little has been put forward in using formal specifications, with the consequent possibility for mis-i...
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| Other Authors: | , , |
| Format: | article |
| Language: | eng |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10400.22/6816 |
| Country: | Portugal |
| Oai: | oai:recipp.ipp.pt:10400.22/6816 |
| Summary: | Over the past decades several approaches for schedulability analysis have been proposed for both uni-processor and multi-processor real-time systems. Although different techniques are employed, very little has been put forward in using formal specifications, with the consequent possibility for mis-interpretations or ambiguities in the problem statement. Using a logic based approach to schedulability analysis in the design of hard real-time systems eases the synthesis of correct-by-construction procedures for both static and dynamic verification processes. In this paper we propose a novel approach to schedulability analysis based on a timed temporal logic with time durations. Our approach subsumes classical methods for uni-processor scheduling analysis over compositional resource models by providing the developer with counter-examples, and by ruling out schedules that cause unsafe violations on the system. We also provide an example showing the effectiveness of our proposal. |
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