A many-core overlay for high performance embedded computing on FPGAS

In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The overlay was evaluated with matrix multiplication, LU decompositio...

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Bibliographic Details
Main Author: Véstias, Mário (author)
Other Authors: Neto, Horácio (author)
Format: conferenceObject
Language:eng
Published: 2018
Subjects:
Many-core overlay
High-performance
Sobreposição de núcleos
Alta performance
Online Access:http://hdl.handle.net/10400.21/9166
Country:Portugal
Oai:oai:repositorio.ipl.pt:10400.21/9166
Description
Summary:In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The overlay was evaluated with matrix multiplication, LU decomposition and Fast-Fourier Transform (FFT) on a ZYNQ-7020 FPGA platform. The results show that using a system-level many-core overlay avoids complex hardware design and still provides good performance results.

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