| Summary: | In recent years, there has been a rapid increasein the use of microprocessor-based systems incritical areas where failures imply risks to humanlives, the environment or expensive equipment. Onesolution for avoiding a possible disaster lays in theuse of dependable systems, able to tolerate andeventually correct faults, requiring high qualityvalidation & verification in their development cycle.The PhD thesis here described aims to contribute amethodology that reuses a proposed standard debug& test infrastructure (NEXUS 5001) to access themicroprocessor core with the objective of supportingthe validation and verification steps of the faulttolerantmechanisms through fault injectioncampaigns. For the purpose of later demonstratingthe proposed methodology, a target microprocessoravailable as a synthesisable core for programmablecomponents will be used. This aspect is crucialbecause it allows us to implement a prototype fordemonstration purposes on a reconfigurable device.From these elements a fault injection infrastructurethat can be utilized not only for validating the faulttolerantcharacteristics of microprocessors but alsofor debugging and data collecting operations will bedeveloped.
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