| Resumo: | In recent years, many coarse-grained reconfigurable architectures have been proposed as programmable accelerators for general purpose processors. The processing elements (PEs) of such architectures mainly differ on the computations they can directly support. Although different PEs and different interconnect resources among them are usually justified by the results presented, there have been few generic approaches able to exploit different PE computing structures while maintaining the same compilation flow. This paper shows our recent achievements concerning a design space exploration tool for an array of coarse-grained PEs. Our approach uses Rewriting Logic to map computations described by imperative software programming languages to the PEs of the target architecture, a VHDL generation step to prototype the architectures being exploited and a clock cycle-based simulator in order to achieve first assessments about the performance of the exploited architectures. Our approach can retarget different PEs structures and complexities, and can be used to evaluate design solutions. In order to show the potential of our approach, we present results on exploiting a 1-D coarse-grained reconfigurable array as an accelerator and the effects of different PEs structures and complexities.
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