Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA
Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA...
| Autor principal: | |
|---|---|
| Outros Autores: | |
| Formato: | conferenceObject |
| Idioma: | eng |
| Publicado em: |
2016
|
| Assuntos: | |
| Texto completo: | http://hdl.handle.net/10400.21/6016 |
| País: | Portugal |
| Oai: | oai:repositorio.ipl.pt:10400.21/6016 |