Composing Families of Timed Automata
Featured Timed Automata (FTA) is a formalism that enables the verification of an entire Software Product Line (SPL), by capturing its behavior in a single model instead of product-by-product. However, it disregards compositional aspects inherent to SPL development. This paper introduces Interface FT...
Autor principal: | |
---|---|
Outros Autores: | , |
Formato: | conferencePaper |
Idioma: | eng |
Publicado em: |
2017
|
Assuntos: | |
Texto completo: | http://hdl.handle.net/1822/69302 |
País: | Portugal |
Oai: | oai:repositorium.sdum.uminho.pt:1822/69302 |