Composing Families of Timed Automata
Featured Timed Automata (FTA) is a formalism that enables the verification of an entire Software Product Line (SPL), by capturing its behavior in a single model instead of product-by-product. However, it disregards compositional aspects inherent to SPL development. This paper introduces Interface FT...
Main Author: | |
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Other Authors: | , |
Format: | conferencePaper |
Language: | eng |
Published: |
2017
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Subjects: | |
Online Access: | http://hdl.handle.net/1822/69302 |
Country: | Portugal |
Oai: | oai:repositorium.sdum.uminho.pt:1822/69302 |