Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design

Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obta...

Full description

Bibliographic Details
Main Author: Falcao, Gabriel (author)
Other Authors: Gomes, Marco (author), Silva, Vítor (author), Sousa, Leonel (author), Cacheira, João (author)
Format: article
Language:eng
Published: 2012
Subjects:
LDPC decoding
DVB-S2
VLSI
ASIC
memory tiling
semi-parallel architecture
M-factorizable architecture
Low-power consumption
high-throughput
Online Access:http://hdl.handle.net/10316/102728
Country:Portugal
Oai:oai:estudogeral.sib.uc.pt:10316/102728

Internet

http://hdl.handle.net/10316/102728

Similar Items