Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design

Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obta...

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Detalhes bibliográficos
Autor principal: Falcao, Gabriel (author)
Outros Autores: Gomes, Marco (author), Silva, Vítor (author), Sousa, Leonel (author), Cacheira, João (author)
Formato: article
Idioma:eng
Publicado em: 2012
Assuntos:
LDPC decoding
DVB-S2
VLSI
ASIC
memory tiling
semi-parallel architecture
M-factorizable architecture
Low-power consumption
high-throughput
Texto completo:http://hdl.handle.net/10316/102728
País:Portugal
Oai:oai:estudogeral.sib.uc.pt:10316/102728

Texto Completo

http://hdl.handle.net/10316/102728

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