Design and simulation of a RISC-V dual-core lockstep for fault tolerant systems
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| Formato: | masterThesis |
| Idioma: | eng |
| Publicado em: |
2020
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| Texto completo: | http://www.repositorio.jesuita.org.br/handle/UNISINOS/9456 |
| País: | Brasil |
| Oai: | oai:www.repositorio.jesuita.org.br:UNISINOS/9456 |