General model for the deployment of time-delay elements in transistorized electronic circuits

This paper presents a general model for the analysis of time-delay contributions due to right half plane (RHP) zeros in circuit's transfer functions. The presence of these RHP zeros is in general associated to Miller capacitances. These can be explored as a means of implementation of delay elem...

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Bibliographic Details
Main Author: Alves, L. N. (author)
Other Authors: Barbosa, L. (author), Aguiar, R.L. (author)
Format: conferenceObject
Language:eng
Published: 1000
Subjects:
Online Access:http://hdl.handle.net/10773/5210
Country:Portugal
Oai:oai:ria.ua.pt:10773/5210