General model for the deployment of time-delay elements in transistorized electronic circuits

This paper presents a general model for the analysis of time-delay contributions due to right half plane (RHP) zeros in circuit's transfer functions. The presence of these RHP zeros is in general associated to Miller capacitances. These can be explored as a means of implementation of delay elem...

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Detalhes bibliográficos
Autor principal: Alves, L. N. (author)
Outros Autores: Barbosa, L. (author), Aguiar, R.L. (author)
Formato: conferenceObject
Idioma:eng
Publicado em: 1000
Assuntos:
Texto completo:http://hdl.handle.net/10773/5210
País:Portugal
Oai:oai:ria.ua.pt:10773/5210