A modular architecture for BIST of boundary scan boards

A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructur...

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Bibliographic Details
Main Author: José M. M. Ferreira (author)
Other Authors: Filipe S. Pinto (author), José S. Matos (author)
Format: book
Language:eng
Published: 1992
Subjects:
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Online Access:https://repositorio-aberto.up.pt/handle/10216/84586
Country:Portugal
Oai:oai:repositorio-aberto.up.pt:10216/84586

Internet

https://repositorio-aberto.up.pt/handle/10216/84586

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