A modular architecture for BIST of boundary scan boards
A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructur...
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| Outros Autores: | , |
| Formato: | book |
| Idioma: | eng |
| Publicado em: |
1992
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| Assuntos: | |
| Texto completo: | https://repositorio-aberto.up.pt/handle/10216/84586 |
| País: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/84586 |
| Resumo: | A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool. |
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