A many-core overlay for high performance embedded computing on FPGAS
In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The overlay was evaluated with matrix multiplication, LU decompositio...
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| Format: | conferenceObject |
| Language: | eng |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10400.21/9166 |
| Country: | Portugal |
| Oai: | oai:repositorio.ipl.pt:10400.21/9166 |