| Resumo: | This paper presents a novel on-line test method for partial and dynamically reconfigurable FPGAs, based on the active replication of configurable logic blocks (CLBs). Each CLB in the FPGA is released for test and again made available to be reused if fault-free, or removed from operation if faulty. The proposed method continuously scans the whole FPGA without disturbing system operation. It implies a very low overhead at chip level, since all the test actions are carried out through the IEEE 1149.1 standard boundary-scan architecture and test access port. Moreover, it presents the additional benefit of correcting transient faults, such as single event upsets in space environments, which would otherwise become permanent faults and most likely introduce functional restrictions or even halt the system.
|
|---|