Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems
This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a ve...
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| Outros Autores: | , |
| Formato: | conferenceObject |
| Idioma: | eng |
| Publicado em: |
2020
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| Assuntos: | |
| Texto completo: | http://hdl.handle.net/10400.21/12300 |
| País: | Portugal |
| Oai: | oai:repositorio.ipl.pt:10400.21/12300 |
| Resumo: | This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The considered methodology adopts a simple and efficient core interconnection mechanism to easily allow the inclusion and the removal of such optimized processing cores. Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology. For the considered system, speedup factors greater than 15 were obtained with a very modest increase of the involved hardware resources. |
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