Hardware solutions for message scheduling in fieldbus system
In a fieldbus system, where several messages must respect temporal constraints, the use of a scheduler is almost obligatory. This work presents an attempt to achieve an execution time reduction of a planning scheduler through the implementation of a co-processor in hardware. Using programmable logic...
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| Format: | masterThesis |
| Language: | eng |
| Published: |
2019
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| Online Access: | http://hdl.handle.net/10773/25736 |
| Country: | Portugal |
| Oai: | oai:ria.ua.pt:10773/25736 |
| Summary: | In a fieldbus system, where several messages must respect temporal constraints, the use of a scheduler is almost obligatory. This work presents an attempt to achieve an execution time reduction of a planning scheduler through the implementation of a co-processor in hardware. Using programmable logic (specifically FPGAs), one takes advantage of the time parallelism possible in hardware to implement a scheduler with given proof and with software implementation in a real fieldbus system. The scheduler adopts the planning scheduler paradigm and is optimised for the FTT-CAN protocol. Aiming its use with low processing power microcontrollers, the co-processor enables a greater performance, enabling an easy integration with existing FTTCAN systems and allowing a minimal hardware modification on the overall system. |
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