Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs
This paper discusses the design and performance of all-digital clock and data recovery mechanisms integrated in low-cost PLDs. Two designs have been explored and analyzed, using data sampling systems with phase detection and decision logic to select either the most appropriate sample as the recovere...
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| Formato: | article |
| Idioma: | eng |
| Publicado em: |
2005
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| Texto completo: | http://hdl.handle.net/10773/7978 |
| País: | Portugal |
| Oai: | oai:ria.ua.pt:10773/7978 |