Aguiar, R. L., & Figueiredo, M. (2005). Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs.
Chicago Style (17th ed.) CitationAguiar, Rui L., and Mónica Figueiredo. Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs. 2005.
MLA (8th ed.) CitationAguiar, Rui L., and Mónica Figueiredo. Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs. 2005.
Warning: These citations may not always be 100% accurate.