Combining rewriting-logic, architecture generation, and simulation to exploit coarse-grained reconfigurable architectures
In recent years, many coarse-grained reconfigurable architectures have been proposed as programmable accelerators for general purpose processors. The processing elements (PEs) of such architectures mainly differ on the computations they can directly support. Although different PEs and different inte...
| Autor principal: | |
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| Outros Autores: | , , |
| Formato: | book |
| Idioma: | eng |
| Publicado em: |
2008
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| Assuntos: | |
| Texto completo: | https://hdl.handle.net/10216/67552 |
| País: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/67552 |