Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test...
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| Outros Autores: | , |
| Formato: | book |
| Idioma: | eng |
| Publicado em: |
1992
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| Assuntos: | |
| Texto completo: | https://repositorio-aberto.up.pt/handle/10216/84575 |
| País: | Portugal |
| Oai: | oai:repositorio-aberto.up.pt:10216/84575 |
| Resumo: | The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable. |
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