Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems

“Copyright © [2001] IEEE. Reprinted from 8th IEEE International Conference on Electronics, Circuits and Systems. ISBN:0-7803-7057-0. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this materia...

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Bibliographic Details
Main Author: Fonseca, José A. (author)
Other Authors: Martins, Ernesto V. (author), Neves, P.A.C.S. (author)
Format: conferenceObject
Language:eng
Published: 2011
Subjects:
Hardware co-processor
FPGA - Fiel Programmable Gate Arrays
Controller area network
Message scheduling in fieldbus systems
Fieldbus
Online Access:http://hdl.handle.net/10400.11/527
Country:Portugal
Oai:oai:repositorio.ipcb.pt:10400.11/527
Description
Summary:“Copyright © [2001] IEEE. Reprinted from 8th IEEE International Conference on Electronics, Circuits and Systems. ISBN:0-7803-7057-0. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.”

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