Sparse matrix multiplication on a reconfigurable many-core architecture
Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality re...
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| Outros Autores: | , , |
| Formato: | conferenceObject |
| Idioma: | eng |
| Publicado em: |
2016
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| Assuntos: | |
| Texto completo: | http://hdl.handle.net/10400.21/6015 |
| País: | Portugal |
| Oai: | oai:repositorio.ipl.pt:10400.21/6015 |
| Resumo: | Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs. |
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