| Summary: | This dissertation presents a study made of the video coding standard AV1. The research provides statistical results referring to various encoding options, such as the most commonly used Transform kernel, vector sizes, the number of bits used in cosine approximations, amongst others. With the gathered results, optimization measures were implemented on the reference encoder, achieving a 3% decrease in the total encoding time, with 81% reduction in the memory used to store cosine coefficients. The algorithm implemented in software was then described in VHDL, obtaining two implementable architectures. The first allows a high degree of parallelization, obtaining all transformed vector sizes within 22 clock cycles, being able to maintain FHD video at 30 frames per second, at an operating frequency of 187 MHz. The second minimizes the amount of logic, although it does not allow the calculation of multiple vector sizes in parallel. This implementation was synthesized and tested on a Nexys 4 board, occupying 79.93% of total FPGA area and 50 mW consumption. On the hardware kit on which it was implemented, this architecture is able to process HD video at 30 frames per second.
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