DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs
A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPG...
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| Outros Autores: | , , |
| Formato: | article |
| Idioma: | eng |
| Publicado em: |
2017
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| Assuntos: | |
| Texto completo: | http://hdl.handle.net/10400.22/9716 |
| País: | Portugal |
| Oai: | oai:recipp.ipp.pt:10400.22/9716 |
| Resumo: | A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming. |
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