Compiling the $\pi$-calculus into a Multithreaded Typed Assembly Language

Current trends in hardware made available multi-core CPU systems to ordinary users, challenging researchers to devise new techniques to bring software into the multi-core world. However, shaping software for multi-cores is more envolving than simply balancing workload among cores. In a near future (...

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Detalhes bibliográficos
Autor principal: Cogumbreiro, Tiago (author)
Outros Autores: Martins, Francisco (author), Vasconcelos, Vasco T. (author)
Formato: report
Idioma:por
Publicado em: 2009
Texto completo:http://hdl.handle.net/10451/14195
País:Portugal
Oai:oai:repositorio.ul.pt:10451/14195
Descrição
Resumo:Current trends in hardware made available multi-core CPU systems to ordinary users, challenging researchers to devise new techniques to bring software into the multi-core world. However, shaping software for multi-cores is more envolving than simply balancing workload among cores. In a near future (in less than a decade) Intel prepares to manufacture and ship 80-core processors; programmers must perform a paradigm shift from sequential to concurrent programming and produce software adapted for multi-core platforms. In the last decade, proposals have been made to compile formal concurrent and functional languages, notably the $\pi$-calculus, typed concurrent objects, and the $\lambda$-calculus, into assembly languages. The last work goes a step further and presents a series of type-preserving compilation steps leading from System F to a typed assembly language. Nevertheless, all theses works are targeted at sequential architectures. This paper proposes a type-preserving translation from the $\pi$-calculus into MIL, a multithreaded typed assembly language for multi-core/multi-processor architectures. We start from a simple asynchronous typed version of the $\pi$-calculus and translate it into MIL code that is then linked to a run-time library (written in MIL) that provides support for implementation of the $\pi$-calculus primitives (e.g., queuing messages and processes). In short, we implement a message-passing paradigm in a shared memory architecture